1. Field of the Invention
The present invention relates to a data accessing system and a data accessing method, and more specifically, to a data accessing system and a data accessing method applied to an LCD display IC for saving routing space area and power consumption.
2. Description of the Prior Art
LCD monitors and related display apparatuses are small and light-weighted display devices, which can be found in many electronic products and are commonly applied to many fields nowadays. For example, in addition to aviation industry and medical equipment industry, they are utilized in portable communication devices, laptop computers, and digital cameras. The LCD monitors can offer flat, detailed, and high-resolution displays with high color contrast and high screen refresh rate. As to most of electronic products using the LCD monitors and having limited power provided by the battery devices, such as portable communication devices, how to provide LCD monitors with high power efficiency, low production cost, and smaller size to meet user's requirements has become a key issue of the future display apparatus development.
Please refer to FIG. 1. FIG. 1 is a block diagram of a data accessing system 100 in accordance with a LCD display IC of the prior art. The data accessing system 100 comprises a data storage device 110 and a source device 120. The data storage device 110 comprises a memory 112 and a register module 114, and the source device 120 has a source driver 122 and a register module 124, wherein the register module 114 contains a plurality of latches 114_1-114—n and the register module 124 contains a plurality of latches 124_1-124—n. The memory 112 in the data accessing system 100 is used for storing digital data corresponding to color components R, G, B of each pixel. For instance, digital data associated with one color component R, G, or B of a pixel contain 6-bit. In other words, suppose that each row of the memory 112 stores digital data of 176 pixels. Because each pixel comprises data of three color components R, G, and B, the bit number of digital data representative of each pixel is 18 (i.e., 6*3). Therefore, the bit number of each row in the memory 112 is 3168 (i.e., 176*18). In addition, the source driver 122 in the source device 120 refers to the pixel data provided by the memory 112 to drive the display panel (not shown) of the LCD monitor to show images corresponding to the pixel data. Please note that operations of the above memory 112 and the source driver 122 are well known to those skilled in this art, and further description is omitted here for the sake of brevity.
In the prior art data accessing system 100, each row of data in the memory 112 is accessed and latched in respective latches 114_1-114—n of the register module 114 through transmission lines a1-an. As mentioned above, if each of the latches 114_1-114—n is able to latch one bit, the register module 114 needs 3168 (i.e., n=176*8) latches to latch a complete row of pixel data. Next, each latch in the register module 114 transmits digital data buffered therein to a corresponding latch in the register module 124 of the source device 120 through a transmission line. It should be noted that because the register module 114 in the present example contains 3168 latches, the prior art data accessing system 100 requires 3168 transmission lines (shown by L1-Ln in FIG. 1) coupled between the register modules 114 and 124. This results in a large routing space needed by the data accessing system 100. Similarly, the register module 124 in the source device 120 also contains latches 124_1-124—n of the same number as that of the corresponding latches 114_1-114—n. When the latches 124_1-124—n have received a complete row of digital data transmitted from the register module 114, the register module 124 transmits the received row of digital data to the source driver 122. The source driver 122 then activates the following image processing according to the received row of digital data, thereby achieving the objective of driving pixels at each scan line of the back-end display panel.
As mentioned above, the prior art LCD display IC requires 3168 transmission lines coupled between the data storage device 110 and the source device 120 to transmit data. In this way, not only is the circuit layout area needed by the LCD display IC increased, but also the cost of routing traces is increased. Furthermore, when data are transmitted via too many transmission lines, the total load of the transmission lines is increased, raising the overall power consumption and degrading the performance of the LCD display IC.
Please refer to FIG. 2. FIG. 2 is a block diagram of a data accessing system 200 in accordance with another LCD display IC of the prior art. The data accessing system 200 comprises a memory 212, a memory bus 223 capable of delivering data-bit of one pixel per bus cycle, and a source device 220. The source device 220 comprises a source driver 222, a register module 224, and a latch control shift unit 226, wherein the register module 224 comprises a plurality of latches 224_1-224—n similar to the latches 124_1-124—n shown in FIG. 1, and the latch control shift unit 226 comprises a plurality of shift registers 226_1-226—n used for inputting pixel data outputted from the memory 212 into the register module 224. This prior art scheme is able to eliminate direct traces routed from the memory 212 to the source. However, if there are 176 pixels located at each row, the memory 212 has to be accessed 176 times. That is, the memory array is enabled 176 times, increasing the power consumption greatly.